VLSI IMPLEMENTATION OF CHARGE PUMP PLL WITH LOW PHASE NOISE VCO

Prathima S R, N Ramya, Lakshmi K R, Srividya P

Abstract: The paper explains the design of a second order power optimized Phase Locked Loop operating at higher frequency ranges with low noise. It is seen that the demand for frequency synthesizers is increasing, and a good design of the phase locked loop is necessary. The designed circuit operates from 20 to 170 MHz frequency range and can be used in data recovery, generation of clock signals, FM demodulation and in many other applications. The noise generated in the components of the PLL is minimized in order to get maximum efficiency. The PLL has a faster locking range and wide capture range enabling it to operate with lesser noise. The PLL blocks are implemented in Cadence schematic tool using 180nm NMOS and PMOS transistors.

Keywords: PLL, CP-PLL, VCO, MOSFET, FD, PFD

DOI: https://doi.org/10.15623/ijret.2018.0706017