DESIGN OF HIGH PERFORMANCE, LOW POWER MUX USING CIRCUIT LEVEL OPTIMIZATION IN CADENCE

Ambily Babu, D. Ane Delphin, Electa Alice Jayarani A

Abstract: This paper gives an insight into the Cadence design of a high performance, low power 8:1 MUX using 180nm technology. The paper is explained in two phases. First phase gives the simulation of a Xilinx tool generated non-optimized schematic. Second phase proposes a circuit level optimization technique using data correlation to realize the same circuit. Simulation results are compared

Keywords: CMOS, Low Power, Power Reduction, Dynamic Power, Switching Activity, Data Correlation, Power Optimization, MUX

DOI: https://doi.org/10.15623/ijret.2016.0516059