CALL FOR PAPERS :
DEC-2018
| Submission Last Date |
:
|
30-Dec-2018
|
| Acceptance Notification
|
:
|
in 15 days
|
| Publication Date
|
:
|
in 5 days
|
FOR AUTHORS
FOR REVIEWERS
IJRET® PUBLICATIONS
DOWNLOADS
CONTACT US
NEWS & UPDATES
|
ANALYTICAL STUDY OF STRAINED SOI MOSFET
Aditi Varshney, Avtar Singh
Abstract: In this paper, a comparison between Silicon on Insulator (SOI) and Strained Silicon on Insulator (SSOI) has been done with different technology nodes (25 nm& 32nm) .The Physical parameters for the N -channel MOSFET have been specified according to the International Technology Roadmap for Semiconductors (ITRS)[1].Simulations are done in ATLAS package of SIVACO tool. Further in this work, study of SOI Device incorporating the concept of strained channel are carried out. Simulation of different values of Drive Current (Ion), Leakage Current (Ioff) and Transfer Characteristics (Id/Vg) are analyzed. All the structures are simulated for Uniaxial Strained SOI MOSFET as well as Biaxial Strained SOI MOSFET in nanometer. It has been found that Strained SOI structure shows larger Drive Current as compare to SOI structures. Hence due to its larger Drive Current it seems to better drive capability as compare to other MOS candidates. In Strained channel MOS devices electrons can move 70% faster allowing Strained Silicon transistors to switch 35% faster.
Keywords: Strained Silicon, Uniaxially & Biaxially Strained-Silicon MOSFET
DOI: https://doi.org/10.15623/ijret.2016.0512009
|
|