VLSI IMPLEMENTATION OF HIGH PERFORMANCE DIGITAL COMPARATOR FOR ANALOG SIGNAL PROCESSING APPLICATION

Ayee Vinotha J, Priyadarshni.S

Abstract: A digital comparator is one of the fundamental computational elements in most digital circuit components such as microprocessor and in digital signal processing designs as well. A new and efficient comparator design featuring with reduced area and power is presented here. The comparator executes its comparison operation from most significant bit to the least significant bit only when the number of comparison bits is equal. The comparator architecture is based on cut set algorithm which reduces the silicon area by time multiplexing many operations into single functional units. This type of algorithm reduces the power dissipation by eliminating unnecessary transitions. In addition, the comparator design is simple and flexible since it makes use of combinational circuitry alone. The main advantage of this design is its low power which can be tapped in digital signal processing applications like analog to digital convertor.

Keywords: Comparator Architecture Cut Set Algorithm, Fully Digital Analog To Digital Convertor

DOI: https://doi.org/10.15623/ijret.2016.0511036