DESIGN AND SIMULATION OF A 32-BIT RISC BASED MIPS PROCESSOR USING VERILOG

Priyavrat Bhardwaj, Siddharth Murugesan

Abstract: This research paper presents design & simulation of a high performance five stage pipelined 32-bit Microprocessor without Interlocked Pipeline Stages (MIPS),which is a Reduced Instruction Set Computing (RISC) architecture based processor. The purpose of RISC microprocessor is to execute a minuscule batch of instructions, with the intention of proliferating the celerity of the processor. This processor was designed with5 phases of pipeline in particular Instruction Fetch (IF), Instruction Decode& Register Fetch (ID), Execution& Address Calculation (EX), Memory Access (MEM) and Write Back (WB) modules. The designing process was done using a myriad of modules which are the ALU, Control Unit, Program Counter, MUX, Instruction Memory, Data Memory, CPU, Register File, Sign Extension. The designing of this processor is developed using the Hardware Description Language (HDL) - Verilog in ModelSim simulator. The supreme aim of this paper is to develop the RTL logic design using Xilinx tool.

Keywords: MIPS, RISC, CISC, Verilog, RTL, ModelSim, Xilinx

DOI: https://doi.org/10.15623/ijret.2016.0511030