SCAN SEGMENTED STUMPS ARCHITECTURE FOR LOW POWER

Sindhu Sidnal, Nayana M, Siva Yellampalli

Abstract: Built-In-Self-Test is one of the technique for test power reduction that uses a scan segmented chains in a CUT the goal of this technique is to minimize the power consumption during test mode. One of the DFT technique is to design a circuit so that the circuit can test itself is called BIST which eliminates the need for external ATE. BIST architectures may results in increased test power and reduced fault coverage. This paper proposes a new test power reduction technique for BIST. The idea is to reduce the number of shift cycles required to test the CUT by dividing the scan chain into number of segments and only two segments will be triggered at a time. The BIST environment is implemented by taking S15850 benchmark circuit as CUT and it achieved 21% reduction in test power.

Keywords: TPG, CUT, ORA, ROM, MISR, STUMPS

DOI: https://doi.org/10.15623/ijret.2016.0507073