ENHANCING PERFORMANCE OF NOC BY EMPLOYING FAULT TOLERANT ROUTING ALGORITHM

Shrushti Tapar, Jinal Tapar, Aashish B Kharate

Abstract: In the state-of-art of high performance computing, Network on chip (NoC) is emerging as a new trend for inter-connection solutions to dense System on chip (SoC) design. The key advantages of NoC are high performance and scalability. Despite those improvements over the conventional shared-bus based systems, NoC are not shown as the ideal solution for the future SoC. Recently, with the three dimension (3D) technology, the 3D NoC has been designed to overcome the high power consumption, high cost communication and low throughput. In this project, 3x3x2 virtual channel router with mesh topology connection is to be designed and synthesized using Xilinx EDA tools. A 3D router design which can support at maximum seven requests simultaneously depending upon location of router in NoC. This 3D model is natural extension of 2D mesh NoC. The routing algorithm will be the Look Ahead –XYZ routing which is simple and free of deadlocks and enhances system performance by reducing packet delay. This will be suitable for ultra high speed application with low latency and low power consumption. Here in this project system is simulated using VHDL and implemented on FPGA kit of Virtex 5 LX110T.

Keywords: SoC, NoC, LA-XYZ, FTLA -XYZ

DOI: https://doi.org/10.15623/ijret.2016.0504046