VERIFICATION OF AMBA AXI BUS PROTOCOL IMPLEMENTING INCR AND WRAP BURST USING SYSTEM VERILOG

Harsha Garua, Keshav Sharma, Chusen Duari

Abstract: This paper describes the development of verification environment for AMBA AXI (Advanced Extensible Interface) protocol using System Verilog. AXI supports high performance, high-frequency system designs. It is an On-Chip communication protocol. It is suitable for high-bandwidth and high frequency designs with minimal delays. It provides flexibility in the implementation of interconnect architectures and avoid use of complex bridges. It is backward-compatible with existing AHB and APB interfaces. The key features of the AXI protocol are that it consists of separate address, control and data phases. It support unaligned data transfers using byte strobes. It requires only start address to be issued in a burst-based transaction. It has separate read and write data channels that provide low-cost Direct Memory Access (DMA). This paper is aimed at the verification of various burst type transaction (INCR and WRAP) of the AXI bus protocol and the Verification Environment is built using System Verilog coding[1]

Keywords: AMBA AXI, INCR, Wrap Burst, System Verilog

DOI: https://doi.org/10.15623/ijret.2016.0503041