DESIGN AND IMPLEMENTATION OF SAD ALGORITHM FOR MOTION ESTIMATION IN H.264/AVC

Geethanjali G, William Thomas

Abstract: Video – telephony, video conferencing and video streaming to mobile phones via internet, in order to use effectively, the video is often compressed for low memory and fast transfer of video and then decompressed for use Motion Estimation is the power hungry block in the Video Compression System (VCS). The motion estimation operation determines the motion vectors, giving the best direction of the motion, and the “fitness” of that motion vector. Here the new low power full adder cell for low power applications is identified and is used in the proposed sum of absolute difference algorithm, the designs are implemented using ASIC flow, which results in 28.74% improvement in Leakage Power (LP) 12.201% improvement in Dynamic Power (DP) and 13.143% improvement in the total power even though the no of cells increased from 3933to 4501. This paper introduces a basic hardware component “comparator” for the compression architectures. Comparator augments as general purpose core to Sum of Absolute difference (SAD) architecture used for the object recognition, generation of disparity maps of the stereo images and for estimating the motion in videos.

Keywords: H.264/AVC, SAD, ADDER, COMPARATOR, LP, DP, DIGITAL SIGNAL PROCESSING, LOW PWER VLSI

DOI: https://doi.org/10.15623/ijret.2015.0417022