THE DESIGN & SIMULATION OF LOW NOISE AMPLIFIER FOR 1 -2.8 GHZ USING ALN SUBSTRATE

Rajesh V. Navagare, Kishor G. Sawarkar

Abstract: In this paper, we have designed low noise amplifier using 2 stage Cascade topology. We have focused on intermediate matching network design of amplifier for low noise figure and selection of transistor PHEMT is based on noise figure as well as quiescent point required for 0 grid voltage so that amplifier will need only single DC supply i.e. Vdd. Depends upon different topologies used for LNA design with wide band requirement, we chose cascaded topology for good gain with low noise amplifier and optimized for greater bandwidth. Practical inductors are bulky as well as counter intuitive elements for high frequency as they behave as capacitors and to reduce S11. Several windings in inductors make them resistive which increases noise by 0.2-0.4 dB. So we proposed inductor-less input matching network for both stages so that we can increase bandwidth as well as perfect match for low noise figure. This LNA is designed using Advanced Design System (ADS) software to provide 0.5 dB noise figure with power gain of 25 dB and 1-2.5 GHz Bandwidth. So it can be used an L-Band satellite modem that is used in an asset tracking application. Layout is designed using muruta manufacturing lumped components and Aluminum Nitride (AlN) substrate having high dielectric constant and high thermal conductivity.

Keywords: LNA, PHEMT, ADS, AlN

DOI: https://doi.org/10.15623/ijret.2015.0411056