COMPARATIVE ANALYSIS OF LECTOR AND STACK TECHNIQUE TO REDUCE THE LEAKAGE CURRENT IN CMOS CIRCUITS

Mansi Gangele, K. Pitambar Patra

Abstract: CMOS is the latest technology available in today’s world. And the biggest advantage of this technology is it does not consume any power. So the total power consumption is dependent on its leakage power. Since leakage exists in the circuit even if it is in stand by state i.e. the state in which gate of the circuit is not getting power supply. So the power loss in the circuit is high. And that’s why our major concern is to reduce the leakage current in the circuit. Varieties of different techniques are available to reduce the leakage current and still continue to derive more, better techniques. In this paper two different techniques LECTOR and STACK technique which are based on the same principle have been comparatively analyzed.

Keywords: Delay, Leakage current, Lector technique, Stack technique

DOI: https://doi.org/10.15623/ijret.2015.0407015