DESIGN AND IMPLEMENTATION OF 15-4 COMPRESSOR USING 1-BIT SEMI DOMINO FULL ADDER AT 28NM TECHNOLOGY

G.Raju, S.Aruna, G.Ranjith Kumar, S.Vasu Krishna

Abstract: In this paper, we present 15-4 Compressor for Digital signal processing. A new Low power full adder and 5-3 compressor are used in this 15-4 compressor. Full Adder and 5:3 compressors are realized by Semi Domino logic which is faster and consumes less power than other conventional logics. Objective of this Work is to inspect the power, delay, power delay product of full adders in different logic styles and to inspect power, delay, and power delay product of Semi domino 5-3 compressor architecture with other architectures. Simulation results demonstrate the superiority of the proposed adder circuit against the pre-proposed adder circuits in terms of power, delay, PDP. The proposed style gets its benefit in terms of power, delay, PDP. The performance of the adder circuits and compressors is based on TSMC 28nm CMOS process models at the supply voltage of 1V, 500MHz frequency evaluated by the comparing of the simulation results obtained from Cadence spectre.

Keywords: Semi Domino Logic, Full adder, 5-3 compressor, power, delay, PDP, TSMC 28nm

DOI: https://doi.org/10.15623/ijret.2015.0406066