IMPLEMENTATION OF 16X16 BIT MULTIPLICATION ALGORITHM BY USING VEDIC MATHEMATICS OVER BOOTH ALGORITHM

Pranita Soni, Swapnil Kadam, Harish Dhurape, Nikhil Gulavani

Abstract: Multiplication is one of the important operation in digital signal processors. The speed of processor depends on the hardware architecture, delay and power. Previously implemented Booths algorithm is not very competent in terms of delay and hardware complexity, therefore we have implemented multiplication algorithm which is efficient over booths algorithm. For multiplication, as number of bit increases the respective delay increases. For efficient processors, delay should be minimum, to avoid increase in delay we require minimum hardware architecture for the processor and Vedic multiplier has minimum hardware architecture. In this paper we have explained 16 bit ‘Urdhva Tiryagbhyam’ Vedic Multiplier and Booth Multiplier and compared on the various parameters such as speed, delay, hardware complexity. These algorithms are executed in VHDL language by using model sim and synthesis is done in Xilinx software. Spartan 3 family FPGA development board is used for hardware implementation of these algorithms

Keywords: Urdhva Tiryagbhyam, Booth, Vedic Multiplier, Spartan 3.

DOI: https://doi.org/10.15623/ijret.2015.0405070