DESIGN OF AREA AND POWER EFFICIENT HALF ADDER USING TRANSMISSION GATE

Ravi Kumar Anand, Kartar Singh, Pankaj Verma, Ashish Thakur

Abstract: This paper gives an idea to reduce power and surface area of half adder circuit using very popular technique i.e. transmission gate. An adder is a digital circuit that performs addition of two numbers. In many computers and other kind of processors, adders are used not only in arithmetic logic unit but also in other parts of the processors where they are used to calculate addresses, table indices and similar operations .in this paper two bit addition has been done using conventional and transmission gate level and power, area and number of transistors are the scope of comparison. According to the simulation result, power and area are reduced by 55.35 % and 40.269% respectively when the circuit is implemented by transmission gate .thus transmission gate has become a very popular and useful technique to implement digital circuits which help to reduce power, surface area as well as number of transistors.

Keywords: Transmission gate (TG), Half adder, CMOS logic gates, Surface area, Power.

DOI: https://doi.org/10.15623/ijret.2015.0404021