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FPGA IMPLEMENTATION OF 4D-PARITY BASED DATA CODING TECHNIQUE
Vijay Tawar, Rajani Gupta
Abstract:
Keywords: 4-D Parity, Dynamic Power, Error Detection and Correction (EDAC) Code, Even Parity, Field Programmable Gate Array (FPGA), Horizontal-Vertical-Diagonal (HVD), Odd Parity, Xilinx.
DOI: https://doi.org/10.15623/ijret.2015.0403099
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