AN EFFICIENT FPGA BASED SPACE VECTOR PULSE WIDTH MODULATION IMPLEMENTATION FOR SERVO CONTROL APPLICATION

M. Kalpana, G. Arumugam

Abstract: This paper focuses on the design of a low power and high performance FPGA based Space Vector Pulse Width Modulation (SVPWM) controller for three phase implementation for Servo control Application. A new method is proposed to realize easy, accurate and high performance SVPWM technique based on FPGA with low resource consumption and reduced execution time than conventional methods. The FPGA based SVPWM generation involves a digital controller implementation to execute the algorithm and DQ reference generator gives reference vector signal to the controller. The controller in turn controls the PLL generator to generate pulse width modulated clock for three phases. The PLL generator is sourced by clock generator. Experimental results are presented for SVPWM architecture synthesized on standard low-cost FPGA chips, showing very good linearity and resolutions up to 1ns.

Keywords: FPGA, PLL Generator, Space Vector Pulse Width Modulation (SVPWM)

DOI: https://doi.org/10.15623/ijret.2015.0403013