IJRET
  • CrossRef
  • Google Scholar
  • ischolar
  • Index Copernicus
  • IJRET
  • Alternate Text
  • IJRET
  • IJRET
  • IJRET
  • Alternate Text
  • IJRET
  • IJRET
  • IJRET
  • IJRET
  • IJRET
  • IJRET
  • IJRET
Authors will receive one hard copy of full paper, individual print certificates and digital certificates, Submit Manuscript

CALL FOR PAPERS : DEC-2018

Submission Last Date :  30-Dec-2018
Acceptance Notification :  in 15 days
Publication Date :  in 5 days
Submit Manuscript Online

FOR AUTHORS

FOR REVIEWERS

IJRET® PUBLICATIONS

DOWNLOADS

CONTACT US

NEWS & UPDATES

Call for Paper Vol-7 Iss-02 Feb-2018

IJRET invites papers from various engineering disciplines for Volume-07 Issue-02, Feb-2018.

Submit Manuscript

Published Vol-07 Iss-01 Jan-18

IJRET Volume-07 Issue-01, Jan-2018 is published now.

Browse Papers

16NM BULK CMOS DOCCCII BASED CONFIGURABLE ANALOG BLOCK DESIGN FOR FIELD PROGRAMMABLE ANALOG ARRAY

Sadia Shireen, Mohd.Faseehuddin

Abstract: Field programmable analog array (FPAA) is a rapidly growing technology for fast prototyping of analog signal processing systems facilitating the quick innovation at industry level with saving in terms of both time and cost. Analog signal processing is much faster and consumes less power than conventional digital signal processing, justifying the need for FPAA. Here we propose a Dual output current controlled current conveyor (DOCCCII) in 16nm bulk CMOS technology using PTM (High Performance 16nm Metal Gate / High-K / Strained-Si parameter) and discuss its characteristic. DOCCCII is superior in design among Current Conveyors because it requires no additional resistance for activation, it has it’s own parasitic resistance tunable through biasing current and has high bandwidth (GHz range). A configurable analog block (CAB) is also proposed which mainly consists of the DOCCCII readily configurable to realize an application. This cab is used here for the realization of 2 nd order filters.

Keywords: FPAA, Configurable Analog Block, DOCCCII, Electronically Tunable Circuit Design

DOI: https://doi.org/10.15623/ijret.2014.0322026

Home | Publication Ethics | Privacy Policy | Terms & Conditions | Refund Policy | Feedback | Contact Us
Copyright © 2012-2018 IJRET Journal All rights reserved