RECONFIGURABLE AND VERSATILE BILRC ARCHITECTURE DESIGN WITH AN AREA AND POWER EFFICIENT TECHNIQUE

R. Hindhuja Priyadharshini, S.Sobana

Abstract: Coarse Grained Reconfigurable Architecture based systems have become increasingly important in these days. In order to handle multiple applications with low area and power requirement ,a new coarse grained reconfigurable architecture (CGRA) is exhibited here. The architecture which is named BilRC, Bilkent Reconfigurable Computer manipulates an execution-triggering mechanism. By mapping real-world applications, the adaptability of the architecture and the computation model are justified. BilRC design is done by using Xilinx and analysis of Area and Power are done. The proposed architecture design can also be implemented by mapping the applications to a 90-nm FPGA array. The model minimizes the configuration size to about 33 times. The design is further developed leading to a new architecture design so as to support multimedia applications. One of the distinguishing features of the proposed BilRC architecture is that the hardware and the programming language are code signed. The simulation results show an increase in the performance by reducing the power consumption to 92%. The design is synthesized with 90-nm technology, and the mapping applications on BilRC run faster than those on FPGA about 2.5 times. The expectation from BilRC is the replacement of FPGAs with BilRC in Coarse Grained Applications.

Keywords: CGRA, FPGA, execution Triggering, BilRC, coarse grain

DOI: https://doi.org/10.15623/ijret.2014.0319134