HIGH PERFORMANCE LOW LEAKAGE POWER FULL SUBTRACTOR CIRCUIT DESIGN USING RATE SENSING KEEPER

D.Sivaranjani, J.Ajayan, S.Sivasankari

Abstract: Dynamic CMOS are widely employed in high-performance CMOS chips due to high speed and less area in comparison with Static CMOS. However, Dynamic CMOS circuits are inherently less noise tolerant than Static CMOS circuits. This problem becomes more severe with aggressive technology scaling into nanometer process, particularly caused by the charge sharing, the sub-threshold leakage current, the power rail noise and the crosstalk noise. Both noise and process variations impact reliability, causing logic errors that can result in system failure. Process variation is defined as “the deviation from intended or designed values for a structure or circuit parameter of concern” parameter of concern”. In this project, a full subtractor circuit is designed and simulated using rate sensing keeper technique with 120nm technology and Vdd=1.2V for improving the timing and noise tolerance also the noise tolerance characteristics of the full subtractor circuit designed using Rate Sensing Keeper is compared with Twin-Transistor, Current Mirror Keeper based full subtractor circuit.

Keywords: charge sharing, rail noise, noise tolerance, rate sensing and timing optimization

DOI: https://doi.org/10.15623/ijret.2014.0319115