DESIGN OF LOW POWER HIGH SPEED LEVEL SHIFTER

G.Srinivasulu, K. Venkata Ramanaiah, K. Padma Priya

Abstract: The leakage power consumption increases with the scaling of the devices and it is expected that the leakage power consumption is important design constraint of total power consumption. In this proposed work, a new configuration of level shifter for low power high speed application has been presented. The proposed circuit have no cross coupled connection, by which there will be reduction in delay. In this work a new level shifter design has introduced at an ultra low core voltage and has wide range of Input/output voltage. This Low power high speed level shifter allows wide Input/output interface voltage applications in CMOS Technology. On an average it shows an improvement of 8% on average power consumption and 77.2% on delay compared with conventional level shifter with a little bit area overhead

Keywords: Average Power consumption, scaling, level shifter, Transmission gate, level shifter, I/O interface

DOI: https://doi.org/10.15623/ijret.2014.0316003