SELF-CHECKING APPROACH FOR REDUCING SOFT ERRORS IN STATES OF FSM

B.Adichenchaiah, S.Arunamastani

Abstract: Due to reduction in device feature size and supply voltages the probability of soft-errors in Finite State Machines’ (FSMs) states has increased dramatically, and the protection against both Single Event Upset (SEU) and Multiple Bit Upsets (MBUs) soft-errors demand for design of fault tolerant FSMs that detect and correct more than one error. Redundancy has been mostly preferred methodology for Error Detection and Correction (EDAC), however selection of one EDAC method is a trade-off between performance and hardware overhead. In this paper, we present an SEU/MEU hardening approach for FSMs’ states through ‘binary-gray’ code for state encoding and a self-checking process that can detect and correct the soft errors in FSM states. Here 8 bit register is used to store the FSM states using ‘binary-gray’ code, this approach can detect errors until the integer value of binary is not equal to integer value of gray for error state, which is a sparse situation. The little overhead of hardware provided by the self checking block implemented in FSM gives 100% error correction. The Experimentation is performed on a 16 state FSM through bit flip fault injection. The simulation results of bit-flip injection into the FSMs’ state registers are analyzed and compared with the existing onehot × m & self-checking method [1].

Keywords: FSMs, SEU, MBUs, EDAC

DOI: https://doi.org/10.15623/ijret.2014.0316001