FPGA IMPLEMENTATION OF ENCRYPTION AND DECRYPTION ALGORITHM BASED ON AES

Shivaraj.G.Nandeni, Sharanagouda.N

Abstract: This paper presents FPGA based implementation scheme of advance encryption standard AES-128 (with 128 bit Key) encryption and decryption algorithm. The advance encryption standard is a symmetric block cipher that is intended to replace DES as the approved standard for a wide range of application. The 128-bit plain text and 128-bit initial key, as well as the 128-bit output of cipher text, are all divided into four 32-bit consecutive units respectively controlled by the clock. The algorithm is designed and synthesized using Xilinx ISE 13.4 simulated by ISim 0.87xd then implemented on Xilinx FPGA devise XC3S500E the result is verified using standard test vectors

Keywords: AES, FPGA, Verilog HDL, cryptography, synthesis

DOI: https://doi.org/10.15623/ijret.2014.0315180