DESIGN OF DUAL MASTER I2C BUS CONTROLLER

Ashwini s. Tadkal, Padmapriya Patil

Abstract: This paper presents an experimental design and implementation of serial data communication using I2C (Inter-Integrated Circuit) multi master and multi slave bus controller using a field programmable gate array (FPGA). The I2C master bus controller was interfaced with slave. This module was designed in Verilog HDL and simulated in Modelsim 10.1c. The design was synthesized using Xilinx ISE Design Suite 14.2. I2C master initiates data transmission and in order slave responds to it. It can be used to interface low speed peripherals like motherboard, embedded system, mobile phones, set top boxes, DVD, PDA’s or other electronic devices.

Keywords: FPGA, I2C, master, Modelsim, serial data communication, slave, Spartan 3AN, Xilinx.

DOI: https://doi.org/10.15623/ijret.2014.0315081