ASSOCIATIVE MEMORY IMPLEMENTATION WITH ARTIFICIAL NEURAL NETWORKS

Santosh Saraf, A. M. Bhavikatti

Abstract: The first description of ANN integrated circuit implements a continuous time analog circuit for AM. The design used a 22 x 22 matrix with 20,000 transistors, averaging 40 transistors per node to implement a Hopfield AM network. The design faced a scalability challenge at higher levels of integration. The paper advocates handling larger problems by a collection of smaller networks or hierarchical solutions, while predicting, “Significantly different connection technologies” as essential for success in larger systems

Keywords: Associative Memory (AM),CMOS (Complementary metal oxide semiconductors),Artificial Neural Network (ANN), Bayesian Memory Module (BMM), Field Programmable Gate Arrays (FPGA).

DOI: https://doi.org/10.15623/ijret.2014.0315028