DESIGN AND VERIFICATION OF PIPELINED PARALLEL ARCHITECTURE IMPLEMENTATION IN FPGA FOR BIT ERROR RATE TESTER

T.ANBUSELVI, A.AROCKIA BAZIL RAJ

Abstract: The principle measure of performance of a data transmission link is Bit Error Rate (BER). A BER testing scheme is introduced to describe the quality of communication interfaces for multi-channel. Bit errors results due to the improper design and implementation of the link or external noisy environment. We present a parallel pipelined architecture which is efficient in power as well as cost. The Universal Asynchronous Receiver/Transmitter (UART)-RS232 standard communication is employed for all the data logging and on/off line analysis. In electronic packaging systems, the signal quality of channels is determined by eye diagram simulation. The tester incorporates a setup of Pseudo Random Binary Sequence (PRBS) generator, detector and error computation block. Point-to-point serial optical link setup is used for measuring the performance of the tester. At the receiver, the data is compared with the local sequence generator. Synchronization is maintained throughout the transmission with the assistance of pilot sequence. The functions of tester are implemented in FPGA virtex5 device by Xilinx. The quality factor of measured error rate is determined using eye-diagram simulation for more than one channel.

Keywords: Bit-error rate (BER), Universal Asynchronous Receiver/Transmitter (UART), Pseudo Random Binary Sequence (PRBS), eye diagram

DOI: https://doi.org/10.15623/ijret.2014.0314006