FPGA BASED HIGHLY RELIABLE FAULT TOLERANT APPROACH FOR NETWORK ON CHIP(NOC)

Jehosheba Margaret.M, Mary Susanna. M, Rajapirian.P

Abstract: Network on chip is an interconnection between several processing elements and routers. There are several possibilities for the occurrence of faults within the network. These faults degrade the performance of the network. In order to increase the performance several fault tolerant methods has been used. They involve themselves in rerouting and hence take longer paths. To make the path shorter, the router architecture has to be modified. The introduction of minimal routing algorithm for faults in the network increases the overall performance of the network. When we use the algorithm, it takes shortest path regardless of the presence of faults. The proposed algorithm is much simpler than the previous existing algorithm. It provides link among the surviving routers in the network. It proves to be more efficient even in the presence of multiple faults. It has the ability to connect the routers both horizontally and orthogonally even in the presence of faults. It has reduced delay over the network. It has proved to be more reliable of 99.5% when multiple faults are found in the network. It can be used in 4x4 mesh topology with six faulty routers to analyse the reliability of network. It also helps to estimate the various parameters such as reliability, latency, speed, area and power

Keywords: Network on Chip, faulty router, fault tolerant algorithm, chip network, faulty link

DOI: https://doi.org/10.15623/ijret.2014.0314005