POWER EFFICIENT AND HIGH THROUGHPUT OF FIR FILTER USING BLOCK LEAST MEAN SQUARE ALGORITHM IN FPGA

M.Devipriya, V.Saravanan, N.Santhiyakumari

Abstract: In silicon on chip technology demands high performance and low power Very Large Scale Integrated Circuit (VLSI) digital signal processing (DSP) systems. The aim of this paper explores the power consumption technique for the architecture of Finite Impulse Response (FIR) adaptive filter. An adaptive FIR filter with Block Least Mean Square (BLMS) algorithm was developed to reduce the power. Distributed arithmetic (DA)-based formulation of BLMS algorithm is used to reduce the area where both convolution operation to compute filter output and correlation operation to compute weight-increment term could be performed by using the same LUT. Thus a DA based implementation of adaptive filter is highly computational and area efficient

Keywords: FIR, FPGA, DSP, DA, VLSI, BLMS

DOI: https://doi.org/10.15623/ijret.2014.0314001