NOVEL FPGA DESIGN AND IMPLEMENTATION OF DIGITAL UP CONVERTER

Vipin George, C.Senthil Singh

Abstract: In our world, communication systems play an important role in day to day life. In wireless and wired communication systems, signals are to be upsampled at the transmitter. Digital up converter (DUC) is a sample rate conversion technique which is widely used to increase the sampling rate of an input signal. The digital up converter converts low sampled digital baseband signal to a pass band signal. In this paper, we are going to design and implement a low noise digital up converter on a FPGA (Field Programmable Gate Array). In digital up converter, the input signal is filtered and converted to higher sampling rate and then it is modulated with the carrier signal generated from the direct digital synthesizer (DDS). This system consists of a cascaded integrator comb (CIC) interpolation filter, cascaded integrator comb compensation filter, multiplier and a direct digital synthesizer. The cascaded integrator comb interpolation filter performs upsampling of the input signal and the cascaded integrator comb compensation filter is used to compensate the losses of CIC filter by filtering the input signal. The multiplier is used for multiplying the upsampled signal from CIC filter with the carrier signal generated from DDS and gives the DUC output. In this DUC, the input signal is upsampled at the rate of eight. Here, two digital up converters are used and connected with an adder in order to obtain a low noise output signal. The coding of this work is done in VHDL. The simulation and functional verification is carried out using Xilinx ISE and FPGA implementation is carried out using Virtex 5.

Keywords: Digital Up Converter, Cascade Integrator Comb Filter, Field Programmable Gate Array, Direct Digital Synthesizer

DOI: https://doi.org/10.15623/ijret.2014.0313024