CLOCK-GATED AND ENABLE-CONTROLLED 64-BIT ALU ARCHITECTURE FOR LOW-POWER APPLICATIONS

Mahaveer Singh Sikarwar, Sudha Nair

Abstract: The Arithmetic Logic Unit (ALU) design is very important in any Integrated Circuit based processing system. An ALU is also called the brain of any computing system. The Arithmetic operation and Logic operations are processed by ALU to serve the execution of hardware computing. In the proposed design a 64-bit ALU with clock gating is implemented on FPGA for low power and high speed applications. A low power consuming system offers the benefits like device portability, long battery life, good performance criteria, etc. To achieve low power operational performance various techniques have been proposed in previous works. Modification of hardware design provides the desired low power feature up to some extent of desired performance. The power consumption can also be affected by controlling the duration of the operation of the circuit. The circuit enable control logic provides transition signals to the operational circuit only for the duration until the results are calculated by the circuit. Once the results are generated the circuit activity is disabled. This saves the power consumption during the extra clock operations that is used after the generation of result by the circuit in the signal transition by the intermediate circuit. The Clock gating reduces power by controlling the clock signal activity that in turn controls the transition of logic values in the sub-blocks of the ALU. The power required in the undesired transitions is thus saved. The proposed design is implemented and simulated on Xilinx XC3S500E FPGA and its software simulation is performed on Xilinx ISE Test-bench Simulator.

Keywords: ALU, Clock Gating, Dynamic Power, FPGA, Opcode, Operand, Xilinx ISE etc.

DOI: https://doi.org/10.15623/ijret.2014.0312036