ECG BASED HEART RATE MONITORING SYSTEM IMPLEMENTATION USING FPGA FOR LOW POWER DEVICES AND APPLICATIONS

Neha Joshi, Preet Jain

Abstract: This paper proposes a new design to monitor the Heart Rate from Electrocardiogram (ECG) signal. The proposed design is based on the concept of identifying the voltage level of the R-wave complex component of the ECG signal above a threshold level. A 100 Hertz sample rate is selected to sample the complex ECG signal. A dual-counter based calculation method is used to obtain the mathematical value of Heart Rate. The proposed FPGA based ECG Heart Rate monitoring system can operate with high performance with respect to the low-power and high speed. The system is designed using Verilog hardware design language and Xilinx XC3s500E FPGA.

Keywords: ECG, Sampling, Threshold, Heart Rate, FPGA

DOI: https://doi.org/10.15623/ijret.2014.0312020