A SURVEY OF LOW POWER WALLACE AND DADDA MULTIPLIERS USING DIFFERENT LOGIC FULL ADDERS

R Naveen, K Thanushkodi, Preethi, C Saranya

Abstract: In recent years, power dissipation is one of the biggest challenge in VLSI design. Multipliers are the main source of power dissipation in DSP block. Power of any multiplier can be reduced by designing a full adder which will consume very less power. So a lot of researches have been made to decrease the power consumption of the full adder. Here a structured approach for analysing the Wallace and Dadda multiplier is introduced. These multiplier are designed using existing full adders like 28T,16T,14T, and TGFA. These designs are studied and the analysis is made based on the simulation parameter like no of transistors count and power consumption using micro wind tool.

Keywords: Full Adder, Wallace Tree Multiplier, Dadda Multiplier, Power Consumption

DOI: https://doi.org/10.15623/ijret.2014.0311053