A SIMPLE DESIGN OF VHDL BASED CHESS CLOCK INTEGRATED WITH CHESS BOARD

Sarita Sharma, Aditya Pundir, Manish Kumar Gupta

Abstract: In this paper, we are proposing the simplest algorithm with VHDL code to design a chess clock. This algorithm is based on basic simplified fundamentals of chess game. This design is been made for Modelsim simulator and can easily be implemented using FPGA kit. This algorithm is designed to get the least delays and possibilities of errors. RTL equivalent of this algorithm is also shown in the paper. This design can further be enhanced for multi player chess clocks for multiplayer rapid/blitz chess games.

Keywords: Chess Clock, Technical Chess, Algorithms, VHDL, FPGA

DOI: https://doi.org/10.15623/ijret.2014.0309050