SPEED-POWER EXPLORATION OF 2-D INTELLIGENCE NETWORK-ON-CHIP FOR MULTI-CLOCK MULTI-MICROCONTROLLER ON 28NM FPGA (ZYNQ-7000) DESIGN

Anoop Kumar Vishwakarma, Uday Arun

Abstract: Todays feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at low cost and lower energy consumption. SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The bus arbitration and synchronization of MultiMicrocontroller System-on-Chip (MMSoC) strongly influences the area, power and performance of the entire system as it uses switching. The synchronization is generally done by multi clocking which leads to power consumption. Future MMSoC designs will need novel on-chip communication architectures that can provide scalable and reliable data transport. On-chip network architectures are believed to be the ideal solution to many of today’s SoC interconnection problems. Network-on-Chip (NoC) architectures may adopt design concepts and methodologies from Multi-Processor/Multi-Microcontroller architectures. Nevertheless, silicon implementation of networks requires a different perspective, because network architectures have to deal with the advantages and limitations of the silicon fabric. These characteristics will require new methodologies for both on-chip switch designs as well as routing algorithm designs. We envision that future on-chip systems will be communication-centric, in particular, energy and performance issues in designing the Multi-Processor/Multi-Microcontroller System-on-Chip will become challenging. In our work we have designed a switch-box for MMSoC for bus synchronization. In this paper, we explore several critical aspects in the bus synchronization of MMSoC by using the generic MultiMicrocontroller System-on-Chip architecture as the experimental platform; this paper presents both quantitative and qualitative analysis on bus synchronization for Network-on-Chip (NoC). Commonly, we synchronize data bus only as it is more important over the other buses namely address bus, control bus and status bus. But by synchronizing other buses we can improve the overall performance of the entire Multi-Microcontroller System-on-Chip. New methodologies and solutions are also proposed to achieve better performance and power balance for MMSoCs.

Keywords: SoC, MMSoC, NoC.

DOI: https://doi.org/10.15623/ijret.2014.0309031