SET AND SEU ANALYSIS OF CNTFET BASED DESIGNS IN HARSH ENVIRONMENTS

Ameet Chavan, P. Darpana Reddy

Abstract: Over the past decade CNTFET has become one of the strong contender to replace Silicon by offering high performing power efficient nanoelectronics. However, no study has been published that evaluates CNTFETs based designs for SETs and SEUs due to radiation. This paper presents a comparative analysis of existing designs of latches and logic circuits using CNTFETs (32 nm Stanford models) and MOSFETS (45nm IBM FDSOI) for power, performance and radiation robustness. In the analysis CNTFET logic gate designs demonstrated on an average 45% improved resilience to SETs as compared to MOSFET based designs. CNTFET’s energy and delay metrics for latches showed an improvement by two orders over MOSFETs with higher robustness. In the interconnect crossbar analysis, the CNTFETs implementation showed better resilience in minimizing the effect of SET transients by occupying 25% lesser area and consuming 4 times lower energy than MOSFETs implementation to handle same levels of Qcrit.

Keywords: CNTFETs, Single Event Upset (SEU), Single Event Transient (SET), Radiation Robustness

DOI: https://doi.org/10.15623/ijret.2014.0308070