I-SLIP ALGORITHM FOR LOW LATENCY ON HYBRID NOC ARCHITECTURE

Tejaswini Rajesh Deotare, Prashant R.Rothe

Abstract: With today ASIC technology, a large number of memory can be easily implemented in a single chip. As the fabrication technology continuous to improve smaller feature size, which makes allows increasingly more integration of system onto the single dies. without having the any correct scheduling algorithm, communication between the components can becomes the limiting factor for performance. In this Paper ,we use i-slip scheduling algorithm with mesh router for NOC architecture .The advantages of the algorithm is achieving almost 100% throughput as the result low latency can be provided by desynchronization of the output arbiters . For the reduction of the latency of the latency of the hybrid NOC architecture efficient partition and mapping algorithm is proposed. When compared with the other architecture improvement of 17.6% in latency is been studied.

Keywords: Hybrid NOC architecture, i-slip algorithm, mesh router, throughput, I P cores, mesh architecture.

DOI: https://doi.org/10.15623/ijret.2014.0307087