TRANSFER OF UT INFORMATION FROM FPGA THROUGH ETHERNET INTERFACE

C.Suneetha, S.Deepa Rani

Abstract: FPGA introduced in 1980’s has been replaced the expensive ASIC products in the real time data processing systems. This paper presents a design for an Ethernet-based transfer of UT information to all the sub-systems on Xilinx Spartan™-3E Starter Board through any existing LAN can be employed to maintain timing synchronization of all the systems. A VHDL software application is developed that can communicate with the board. IRIG-B (B120) time coding format received from GPS receiver. All the systems need to communicate with external world. FPGA has work in real time. So, a high speed reliable network called Ethernet is used. In its physical layer we use media independent interface (MII). UDP a network protocol used to implement form physical to transport layer. For real time application timing analysis is done.

Keywords: UT, IRIG-B, UDP, MAC, MII, EHERNET, VHDL.

DOI: https://doi.org/10.15623/ijret.2014.0307074