IMPLEMENTATION AND ANALYSIS OF POWER REDUCTION IN 2 TO 4 DECODER DESIGN USING ADIABATIC LOGIC

Ranjan Kumar Singh, Rakesh Jain

Abstract: This paper presents 2 to 4 decoder structure design using CMOS and adiabatic technique. The paper discussed Power consumption in 2 to 4 decoder circuit using adiabatic technology, because now a day’s power consumption is the important and basic parameters of any kind of digital integrated circuit (IC).And there is a challenge to compensate power and performance to meet the systems requirement, because cost of the system is directly affected by power. It is done through the adiabatic techniques because adiabatic circuits are those circuits which work on the principle of adiabatic charging and discharging and which recycle the energy from output nodes instead of discharging it to ground. In this paper we have reduced the power consumption of 2 to 4 decoder circuit. We have taken a time varying source instead of DC supply and obtained the further results. Conventional CMOS circuits achieve a logic ‘1’ or logic ‘0’ by charging the load capacitor to supply voltage Vdd and discharging it to ground respectively. All simulation result and analysis are performing on 250nm MOSIS technology using tannerEDA tool.

Keywords: Adiabatic process, power consumption, VLSI design, switching activity.

DOI: https://doi.org/10.15623/ijret.2014.0307030