POWER ANALYSIS OF 4T SRAM BY STACKING TECHNIQUE USING TANNER TOOL

Harsh Raj, Rakesh Jain

Abstract: As the technology in electronic circuits is improving, the complexity in these circuits also increases. The complexity in the circuits leads to the need of that type of circuits which are portable and fast circuits. The portability in the electronic circuits are achieved by the use of battery. So we have to develop such type of circuits that consume very less power. The major focus in designing a high performance digital system such as microprocessors and various Digital signal Processors is given to low power design. The main part of any digital system is its memory unit. It is not possible to design a digital system without memory. So we can say that memory is the main part which utilize the maximum power in the system. The most used memory cell in the digital systems is the SRAM cells. They are the static RAM cells. Low-power Random Access Memory (RAM) has seen a remarkable and rapid progress in power reduction. The high density and low power SRAMs are needed for application such as hand held devices, laptops, notebooks, IC memory card because of the fact that they are portable devices and uses batteries for power source so they must consume power as low as possible. The power dissipation reduction is not only due to power supply voltage reduction, but also can be done by low power circuit techniques. It should be designed such that it provides a non- destructive read operation and reliable write operation [1].The proposed 4-Transistor with resistive load memory cell makes use of Stacking effect to reduce the leakage current. The stacking effect is used by switching off the stack transistor when the memory is in ideal mode. So the stacking transistor implemented in the circuit behaves like a switch which remain in off state when the cell is in off state and it remain in ON state when Write or Read operation is performed in the memory cell. The tool used is TANNER EDA for schematic simulation. The simulation technology used is MOSIS 250nm.

Keywords: 4T SRAM, Stacking Effect, Conventional SRAM, TANNER EDA Tool, Tail NMOS

DOI: https://doi.org/10.15623/ijret.2014.0307028