A NOVEL MRPSOC PROCESSOR FOR DISPATCH TIME CURTAILMENT

Parvathy Asokan, Kavitha.V, K.V. Ramakrishnan

Abstract: This paper describes a platform which consists of Multi Reconfigurable Instruction Set Processor System on Chip (MRPSOC). Reconfigurable Instruction set processor (RISP) consists of a microprocessor core that can be extended with reconfigurable logic. RISP and MPSOC are the two methods to improve the performance. By combining both, better results can be achieved. MRPSOC can run applications in parallel and accelerate the performance due to its reconfigurable functional unit (RFU) and at the same time it retains programmability. In this paper, Dynamic Critical Path algorithm is used to extract the custom instructions. In this platform, the critical portions of the code can be executed on RFU. For verifying the efficiency of MRPSoC, a set of instructions are executed in both MRPSoC and MPSoC. Finally, from the experimental results, it is concluded that the dispatch time of executing a set of instructions are curtailed as compared to MPSOC.

Keywords: Reconfigurable Instruction set Processors (RISP), Multi-processor System on Chip (MPSoC), Reconfigurable Processing Unit (RPU), and Reconfigurable Functional Unit (RFU)

DOI: https://doi.org/10.15623/ijret.2014.0307018