A COMPARATIVE STUDY OF FULL ADDER USING STATIC CMOS LOGIC STYLE

Manisha, Archana

Abstract: In this review paper 1-bit CMOS full adder cells are studied using standard static CMOS logic style. The comparison is carried out using several parameters like number of transistors, delay, power dissipation and power delay product (PDP).The circuits are designed at transistor level using180nm CMOS technology. Different full adders are studied in this paper like Conventional CMOS (C-CMOS), Complementary pass transistor logic (CPL), Double pass transistor logic (DPL), Transmission gate (TGA), Transmission function (TFA), New 14T, Hybrid CMOS, HPSC, Pseudo nMOS, GDI full adders.

Keywords: PDP, CMOS full adder, power dissipation, low power, logic style.

DOI: https://doi.org/10.15623/ijret.2014.0306092