LOW POWER SRAM CELL WITH IMPROVED RESPONSE

Anant Anand Singh, A. Choubey, Raj Kumar Maddheshiya

Abstract: In SRAM memory cells power dissipation through standby leakage and dynamic loss is a major problem especially in low power fabrication with modern technology scaling and for high temperature operations. This paper is based on low power operation and delay of SRAM cell. Paper presents a novel technique to reduce dynamic power loss during switching activity. The modified SRAM cells with proposed technique are compared with their basic SRAM cells on CADENCE VIRTUOSO on 90nm technology scale. The average power of SRAM cells decreases and the write delay is also slightly improves compared to their parent architecture at the mentioned scale.

Keywords: Dynamic power loss, leakage current, Power consumption, Standby current, Write delay.

DOI: https://doi.org/10.15623/ijret.2014.0306091