OPTIMIZATION AND IMPLEMENTATION OF PARALLEL SQUARER

Sharath D, Devaraju G, Kavitha Devi C.S

Abstract: This paper describes the low power architecture design which is implemented in digital systems. It focuses on the design and implementation of Parallel Squarer and its optimization at the gate level netlist. The efficient parallel squarer design is optimized at the gate level and the results are obtained. It’s much efficient than the existing system. Parallel squarer architecture is implemented based on Binary squarer algorithm to provide low, power, area and delay with the trade-offs constraints. Simulation, synthesis is done in the Modelsim 6.5 and Xilinx 13.1 v. The gate level netlist simulation and synthesis are done in Cadence Encounter RTL compiler and the results are compared with Xilinx and cadence tool.

Keywords: Binary Squarer, Cadence, Modelsim, Parallel Squarer, etc

DOI: https://doi.org/10.15623/ijret.2014.0306078