DESIGN AND IMPLEMENTATION OF SYNCHRONOUS 4-BIT UP COUNTER USING 180NM CMOS PROCESS TECHNOLOGY

Yogita Hiremath, Akalpita L. Kulkarni, J. S. Baligar

Abstract: In this paper design of synchronous 4-bit up counter is proposed using master-slave negative pulse-triggered D flip-flops. The master slave D flip-flop is implemented using 8 nand gates and an inverter. The counter is provided with additional synchronous clear and count enable inputs. The main objective is to optimize the layout of the synchronous 4-bit up counter in terms of area. The design is implemented using Cadence Virtuoso schematic editor and simulated using Cadence Virtuoso analog design environment at 180nm CMOS process technology. The optimized layout of the counter is designed using Cadence Virtuoso Layout Suite. The counter has transistor count of 210. The estimated power of the counter is 97.90µW and delay is 20.39ns.

Keywords: Area, Cadence, Counter, Delay, Master-slave D flip-flop, Nand gate, Power and Synchronous

DOI: https://doi.org/10.15623/ijret.2014.0305149