TD-AMS PROCESSING FOR VLSI IMPLEMENTATION OF LDPC DECODER

Maramreddy Harish, Neelima Koppala

Abstract: An Efficient analog to digital interface (TDC/DTC) is presented. In particular, we explore time-based techniques for data conversion, which can potentially achieve significant reductions in power consumption while keeping silicon chip area will be very small. On the basis of a generic mixed-signal system the scaling difficulties of analog and mixed-signal circuits based on a signal representation in the voltage domain are discussed for nanometer CMOS technologies. Easy to control and seamlessly embedded, were also low latency occur. Mainly applicant for LDPC implementation which is used for error correcting and image processing will be done. In gate level verilog hardware description language used for coding digital circuits using tool Xilinx ISE 10.1i and target family Spartan 3E,Device XC3S500, speed -5,package:FG320.The synthesized for the proposed digital circuits.

Keywords: low density parity-check (LDPC), time-to-digital converter (TDC), Binary-search time-to digital converter (BS-TDC), low power

DOI: https://doi.org/10.15623/ijret.2014.0305063