AN AREA AND POWER EFFICIENT ON CHIP COMMUNICATION ARCHITECTURES FOR IMAGE ENCRYPTION AND DECRYPTION

Y.Amar Babu, G.M.V.Prasad

Abstract: The design of new electronic systems is getting more complex as more functionality is integrated into these systems. To design complex system, a predictable design flow is needed. A soft processor based System-on-Chip (SoC) is often mentioned as the hardware platform to be used in modern electronics systems for fast prototyping on FPGA. In this paper, a novel area and power efficient on chip communication architectures has been proposed for image encryption and decryption using single soft processor(Micro Blaze). Proposed System On Chip explores On chip Communication architectures features to efficiently implement the application. The SoC offers scalability and guarantees on the timing behavior when communicating data between various processing and storage elements. Proposed SoC has been implemented on Spartan6 FPGA and evaluated at 83.33MHz. It has occupied only 19% of resources available on target FPGA , consumes very low power. The proposed on chip communication architectures compared with device utilization on FPGA and power consumed.

Keywords: SoC, FPGA, Encryption and Decryption, Micro Blaze

DOI: https://doi.org/10.15623/ijret.2014.0305054