IMPLEMENTATION OF A BIT ERROR RATE TESTER OF A WIRELESS COMMUNICATION SYSTEM ON AN FPGA

Lakshmy Sukumaran, Dharani K G

Abstract: This paper deals with the Field Programmable Gate Array (FPGA) implementation of an entire digital baseband wireless communication system. The proposed BER tester (BERT) integrates the modules of a typical communication system along with an AWGN channel into a single FPGA. The BER is calculated for a 2*2 MIMO system also. This FPGA based solution is a more cost effective, flexible and faster solution compared with the commercially available BER test equipments and software based simulators.

Keywords: BER; BERT; MC simulations; FPGA

DOI: https://doi.org/10.15623/ijret.2014.0305020