SELECTIVE FITTING STRATEGY BASED REAL TIME PLACEMENT ALGORITHM FOR DYNAMICALLY RECONFIGURABLE FPGAS

B.Premalatha, S.Umamaheswari

Abstract: Engineers in the field of Advanced computing paradigm struggles to satisfy the demand of high performance applications in terms of speed such as image processing, embedded computing ,video stream processing etc.,. Providing high speed in terms of truly multitasking of reconfigurable computing devices such as FPGAs acts as suitable computing platform for such applications. Two main problems in FPGA to fulfil the requirement are scheduling and placement of incoming hardware tasks. Scheduling and placement are the two process that depends on each other. Improper scheduling affects the placement performance. To the above two things, one more factor called fragmentation related closely that affects performance of FPGAs during placement. The performance metric used in this paper is task rejection ratio. Effective placement algorithm results minimum task rejection ratio. In this paper, we address the problem of real time scheduling and placement of hardware tasks by considering the factor called fragmentation in the objective to minimize the task rejection ratio. We developed an Selective fitting strategy based algorithm and simulation is carried out. Results are compared with basic placement fitting strategy such as first fit, best fit and worst fit. Our algorithm shows better performance in term of task rejection ratio.

Keywords: Dynamically Reconfigurable FPGAs, On-line Scheduling and Placement, Resource management, Task Rejection ratio.

DOI: https://doi.org/10.15623/ijret.2014.0304158