REALIZATION OF HIGH PERFORMANCE RUN-TIME LOADABLE MIPS SOFT-CORE PROCESSOR

Prathibha S R, M Z Kurian

Abstract: Soft-core processors on Field Programmable Gate Array (FPGA) chips are becoming a solution for application-specific customization. Soft-core processors provide several advantages for designer. Currently using microprocessor doesn’t support realtime loading. If, any change in the assembly code of the implemented processor, it requires re-implementation and downloads the softcore on FPGA. This project proposes realization of run-time loading technique of a MIPS (Microprocessor without Interlocked Pipeline Stages) soft- core processor on FPGA. The proposed system consists of mainly three components: microprocessor soft-core, software tool and universal asynchronous Receiver/Transmitter (UART). Since, here MIPS code is updating instantly there is no need of resynthesize, place, route, and reload the soft-core. The software tool communicates between the user and MIPS soft-core processor through UART. Five stage pipelining is included to improve the overall processor performance. In this paper 32-bit MIPS soft-core processor, RAM module, APB Interface is designed and simulated using Modelsim. Design architecture will be doing in Verilog, simulate using Modelsim 10.3 simulator and realize in Spartan-6 FPGA using Xilinx ISE 14.2.

Keywords: FPGA, MIPS, PERL, RISC, UART etc…

DOI: https://doi.org/10.15623/ijret.2014.0304045