EFFICIENT IMPLEMENTATION OF BIT PARALLEL FINITE FIELD MULTIPLIERS

Ajitha.S.S, Retheesh.D

Abstract: Arithmetic in Finite/Galois field is a major aspect for many applications such as error correcting code and cryptography. Addition and multiplication are the two basic operations in the finite field GF (2m ).The finite field multiplication is the most resource and time consuming operation. In this paper the complexity (space) analysis and efficient FPGA implementation of bit parallel Karatsuba Multiplier over GF (2 m ) is presented. This is especially interesting for high performance systems because of its carry free property. To reduce the complexity of Classical Multiplier, multiplier with less complexity over GF (2 m ) based on Karatsuba Multiplier is used. The LUT complexity is evaluated on FPGA by using Xilinx ISE 8.1i.Furthermore,the experimental results on FPGAs for bit parallel Karatsuba Multiplier and Classical Multiplier were shown and the comparison table is provided. To the best of our knowledge, the bit parallel karatsuba multiplier consumes least resources among the known FPGA implementation.

Keywords: Classical Multiplier, Cryptograph, FPGA, Galois field, Karatsuba Multiplier

DOI: https://doi.org/10.15623/ijret.2014.0303122