LOC, LOS AND LOES AT-SPEED TESTING METHODOLOGIES FOR AUTOMATIC TEST PATTERN GENERATION USING TRANSITION DELAY FAULT MODEL

Parth Borda, Pankaj Prajapati

Abstract: Faults, caused by timing-related defects in very large scale integrated circuits, are important to detect to optimize coverage and test time. Delay faults are only due to timing malfunction. At-speed test is only method to detect these delay faults. This paper describes and compares different at-speed testing techniques on vivid point of views along with them practical implementation. This paper also shows results generated by automatic test pattern generation tool for these techniques. Next, generated test patterns are simulated by using simulator and correctness of these methods are verified.

Keywords: LOC (Launch on capture), LOS (Launch on shift), LOES (Launch on extra shift), At-speed testing.

DOI: https://doi.org/10.15623/ijret.2014.0303051